The present invention relates to implementing a user logic design in a programmable logic device, and more particularly, the present invention relates to implementing logic design memory in physical memory devices of a programmable logic device.
Programmable logic devices are well known. Early programmable logic devices were one-time configurable. For example, configuration may have been achieved by “blowing” (i.e., opening) fusible links. Alternatively, the configuration may have been stored in a programmable read-only memory. Those devices generally provided the user with the ability to configure the devices for “sum-of-products” (or “P-TERM”) logic operations. Later, such programmable logic devices incorporating erasable programmable read-only memory (EPROM) for configuration became available, allowing the devices to be reconfigured.
Still later, programmable logic devices incorporating static random access memory (SRAM) elements for configuration became available. These devices, which also can be reconfigured, store their configuration in a nonvolatile memory such as an EPROM, from which the configuration is loaded into the SRAM elements when the device is powered up. These devices generally provide the user with the ability to configure the devices for look-up-table-type logic operations. At some point, such devices began to be provided with embedded blocks of random access memory that could be configured by the user to act as random access memory, read-only memory, or logic (such as P-TERM logic).
Programmable logic devices are becoming more sophisticated with respect to, for example, the types of physical memory devices that they provide. Whereas earlier programmable logic devices provided only a single type of physical memory device, current programmable logic devices may provide multiple options on a single chip. This offers users the flexibility of designing logic without the previous limitation of being restricted to implementing that logic using a single type of physical memory device.
While it may have been possible to program the earliest programmable logic devices manually, simply by determining mentally where various elements should be laid out, it was common even in connection with such earlier devices to provide programming software that allowed a user to lay out logic as desired and then translate that logic into programming for the programmable logic device. With current larger devices, it would be impractical to attempt to lay out the logic without such software.
Known techniques for implementing logic design memory into physical memory devices are limited with respect to several aspects. Known techniques do not take into account the possibility of having more than one type of physical memory device in a single programmable logic device. If, for example, a particular logic device has three or four different types of physical memory devices, each being suited for particular applications, it will typically be left to the user to manually make the determination of which logic design memory to implement in which type of physical memory device.
Another shortcoming of known techniques for implementing logic design memory in physical memory devices is the inability to guarantee that all location constraints will be met and the inability to prevent problems from arising due to conflicting constraints.
Yet another shortcoming of the known techniques is that typically the resultant physical devices are not optimized for efficiency in terms of resource usage, timing constraints, power demand, as well as other factors.
It would therefore be desirable to provide a way in which logic design memory is implemented in programmable logic devices taking into account the type of physical memory devices available in the programmable logic devices.
It would further be desirable to provide a way to optimize how logic design memory is implemented in physical memory devices.